主控模塊程序：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY master IS
PORT(LEFT,RIGHT,BRAKE,FOG,BACK:IN STD_LOGIC;-定義端口
LP,RP,LR,F,B,BRAKE_LED:OUT STD_LOGIC);
END;
ARCHITECTURE ART OF master IS
BEGIN
BRAKE_LED<=BRAKE;-將剎車信號BRAKE給輸出脈沖BRAKE_LED
F<=FOG; -將霧燈模式FOG給輸出脈沖F
B<=BACK; -將倒車模式BACK給輸出脈沖B
PROCESS(LEFT,RIGHT)
VARIABLE TEMP:STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
TEMP:=LEFT&RIGHT;
CASE TEMP IS
WHEN"00"=>LP<='0';RP<='0';LR<='0';
WHEN"01"=>LP<='0';RP<='1';LR<='0';右轉彎輸出脈沖
WHEN"10"=>LP<='1';RP<='0';LR<='0'左轉彎輸出脈沖;
WHEN OTHERS =>LP<='0';RP<='0';LR<='1';無效
END CASE;
END PROCESS;
END ARCHITECTURE ART;
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