library ieee;
use ieee.std_logic_1164.all;
entity quanjian is
port(a,b,c:in std_logic;
sout,jout:out std_logic);
end;
architecture one of quanjian is
signal abc:std_logic_vector(2 downto 0);
begin
abc<=a&b&c;
process(abc)
begin
case abc is
when"000"=> sout<='0';jout<='0';
when"001"=> sout<='1';jout<='1';
when"010"=> sout<='1';jout<='1';
when"011"=> sout<='0';jout<='1';
when"100"=> sout<='1';jout<='0';
when"101"=> sout<='0';jout<='0';
when"110"=> sout<='0';jout<='0';
when"111"=> sout<='1';jout<='1';
when others=>null;
end case;
end process;
end one;
library ieee;
use ieee.std_logic_1164.all;
entity quanjian4 is
port(a11,a12,a13,a14,b11,b12,b13,b14:in std_logic;
s1,s2,s3,s4,j4:out std_logic);
end;
architecture two of quanjian4 is
signal d,e,f:std_logic;
component quanjian
port(a,b,c:in std_logic;
sout,jout:out std_logic);
end component;
begin
u1:quanjian port map(a=>a14,b=>b14,c=>'0',jout=>d,sout=>s4);
u2:quanjian port map(a=>a13,b=>b13,c=>d,jout=>e,sout=>s3);
u3:quanjian port map(a=>a12,b=>b12,c=>e,jout=>f,sout=>s2);
u4:quanjian port map(a=>a11,b=>b11,c=>f,jout=>j4,sout=>s1);
end two;
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