LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ch IS
PORT(clk: IN STD_LOGIC;
q1: out INTEGER RANGE 0 TO 9;
qt: out INTEGER RANGE 0 TO 6;
co: OUT STD_LOGIC);
END ch;
ARCHITECTURE behav OF ch IS
signal q1a: INTEGER RANGE 0 TO 9;
signal qta: INTEGER RANGE 0 TO 6;
BEGIN
PROCESS(clk,q1a)
BEGIN
IF(clk'EVENT AND clk='1') THEN
IF(q1a=9) THEN
q1a<=0;
ELSE
q1a<=q1a+1;
END IF;
q1<=q1a;
END IF;
END PROCESS;
PROCESS(clk,q1a,qta)
BEGIN
IF(clk'EVENT AND clk='1') THEN
IF(q1a=9) THEN
IF(qta=5) THEN
qta<=0;
ELSE
qta<=qta+1;
END IF;
qt<=qta;
END IF;
END IF;
END PROCESS;
PROCESS(clk, q1a, qta)
BEGIN
IF(clk'EVENT AND clk='1') THEN
IF(qta=5 AND q1a=9) THEN
co<='1';
ELSE
co<='0';
END IF;
END IF;
END PROCESS;
END behav;
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