ModelSim仿真源代碼

ID:294494 · 發表于 2018-3-20 15:23

Counter的源代碼：

module lin(clk,rst,in1,in2,cin,count,sum);

input [7:0]in1,in2;

input clk,rst,cin;

output [7:0]sum;

output count;

reg [7:0]sum;

reg count;

always @(posedge clk)

begin

if(!rst)

begin

count<=0;

sum<=8'b0;

end

else

sum<=in1+in2+cin;

if(sum>=8'b11111111)

count<=1;

else

count<=0;

end

endmodule

Tcounter的源代碼：

`timescale 10ns/1ns

module tcounter;

reg clk1, rst1,cin1;

reg[7:0] din1,din2;

wire count1;

wire[7:0] sum1;

lin adder ( .cin (cin1),

.in1 (din1),

.in2 (din2),

.clk (clk1),

.rst (rst1),

.sum (sum1),

.count (count1)

);

initial // Clock generator

begin

clk1 = 0;

forever #10 clk1 = ~clk1;

end

initial

begin

#0 rst1 = 1'b0;

#0.5 rst1 = 1'b1;

#22 rst1 = 1'b0;

end

always @ ( negedge clk1 )

begin

din1 = $random%256;

din2 = $random%256;

cin1 = $random%2;

end

endmodule

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ModelSim仿真源代碼

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