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發布時間: 2019-2-28 18:31
正文摘要:在做一個老師課后布置的小設計,出了兩個錯誤,2天了,我嘗試了各種辦法依舊沒有解決。 元件例化的port ma出錯 不知道各位大佬有何見解 |
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文字版 出錯源代碼 pcreg:flopr generic map(32) port map(clk,reset,pcnext,pc); Error (12006): Node instance "pcreg" instantiates undefined entity "flopr". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP. 下面是flopr的定義...就在出錯代碼的上方。 component flopr generic(width:integer); port(clk,reset: in STD_LOGIC; d: in STD_LOGIC_VECTOR(width-1 downto 0); q: out STD_LOGIC_VECTOR(width-1 downto 0)); end component; |