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標題: 能實現分和秒的時鐘電路 [打印本頁]

作者: 1824380946 時間: 2016-7-12 16:35
標題: 能實現分和秒的時鐘電路
S_SET BIT P1.5
M_SET BIT P1.6
WS EQU 35H
SEC EQU 29H
MIN EQU 30H
TCNC EQU 34H
ORG 0000H
SJMP START
ORG 000BH
LJMP INT_T0
START:MOV DPTR,#TAB
   MOV SEC,#0
MOV MIN,#0
MOV TCNC,#0
MOV TMOD,#01H
MOV TH0,#(65536-50000)/256
MOV TH0,#(65536-50000)MOD 256
MOV IE,#82H
SETB TR0
S1:LCALL DISPLAY
JNB S_SET,A1
JNB M_SET,K1
A1:LCALL DELAY
JB S_SET,S1
INC SEC
MOV A,SEC
CJNE A,#60,J0
MOV SEC,#0
LJMP K1
CC:LCALL DELAY
JB M_SET,S1
K1:INC MIN
MOV A,MIN
CJNE A,#60,J1
MOV MIN,#0
MOV SEC,#0
LJMP S1
J0:JB S_SET,S1
LCALL DISPLAY
SJMP J0
J1:JB M_SET,S1
LCALL DISPLAY
SJMP J1
INT_T0:MOV TH0,#(65536-50000)/256
   MOV TL0,#(65536-50000)MOD 256
INC TCNC
MOV A,TCNC
CJNE A,#20,RETUNE
INC SEC
MOV TCNC,#0
MOV A,SEC
CJNE A,#60,RETUNE
INC MIN
MOV SEC,#0
MOV A,#MIN
CJNE A,#60,RETUNE
MOV MIN,#0
MOV SEC,#0
MOV TCNC,#0
RETUNE:RETI
DISPLAY:MOV A,SEC
      MOV B,#10
  DIV AB
  CLR P3.4
  MOVC A,@A+DPTR
  MOV P0,A
  LCALL DELAY
  SETB P3.4
  MOV A,B
  CLR P3.5
  MOVC A,@A+DPTR
  MOV P0,A
  LCALL DELAY
  SETB P3.5
  MOV A,MIN
  MOV B,#10
  DIV AB
  CLR P3.2
  MOVC A,@A+DPTR
  MOV P0,A
  LCALL DELAY
  SETB P3.2
  MOV A,B
  CLR P3.3
  MOVC A,@A+DPTR
  MOV P0,A
  LCALL DELAY
  SETB P3.3
  RET
DELAY:MOV R6,#10
D1:MOV R7,#250
DJNZ R7,$
DJNZ R6,D1
RET
TAB:DB 3FH,06H,5BH,4FH,66H,6DH,7DH,07H,7FH,6FH
END

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