verilog的邏輯代碼：
module seg_test(
input clk,
input rst_n,
output reg clk_1k
);
reg [19:0] count;
always@(posedge clk or negedge rst_n)
begin
if(rst_n==1'b0)
begin
count<=1'b0;
end
else if(count==20'd49)
begin
clk_1k<=~clk_1k;
count<=1'b0;
end
else
begin
count<=count+1'b1;
end
end
endmodule
test bench代碼：
`timescale 1 ps/ 1 ps
module seg_test_vlg_tst();
reg clk;
reg rst_n;
wire clk_1k;
seg_test i1 (
.clk(clk),
.clk_1k(clk_1k),
.rst_n(rst_n)
);
initial
begin
clk=1'b0;
rst_n=1'b0;
#10;
rst_n=1'b1;
end
always
begin
clk=~clk;
#10;
end
endmodule
