欧美极品高清xxxxhd,国产日产欧美最新,无码AV国产东京热AV无码,国产精品人与动性XXX,国产传媒亚洲综合一区二区,四库影院永久国产精品,毛片免费免费高清视频,福利所导航夜趣136

標題: quartues編寫的計數器 modelsim仿真沒有輸出 [打印本頁]

作者: 2107972907 時間: 2020-5-22 15:29
標題: quartues編寫的計數器 modelsim仿真沒有輸出
quartues編寫的一個計數器，，modelsim仿真時的輸出波形是直線。。付給初值后一直輸出初值，clk顯示正常
激勵文件

library ieee;

use ieee.std_logic_1164.all;

entity clock_tb is

end entity clock_tb;

architecture behaviour of clock_tb is

component clock

port(

clk: in std_logic;

clr: in std_logic;

seg: out std_logic_vector(7 downto 0);

dig: buffer std_logic_vector(2 downto 0)

);

end component;

signal clk:std_logic;

signal clr:std_logic;

signal seg:std_logic_vector(7 downto 0):="01000000";

signal dig:std_logic_vector(2 downto 0):="000";

begin

u1: clock

port map(

clk=>clk,

clr=>clr,

seg=>seg,

dig=>dig);

process begin

wait for 10 ns; clk<='1';

wait for 10 ns; clk<='0';

end process;

process begin

wait for 0 ns;

clr <= '0'; --復位開始

wait for 200.1 ns;

clr <= '1'; --復位完成

wait; --持續等待

end process;

end architecture behaviour;

歡迎光臨 (http://m.raoushi.com/bbs/)