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程序：
--頂層模塊的VHDL
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TOP_ENTITY IS
PORT
(
CLK_IN_1Hz:IN STD_LOGIC;
CLR:IN STD_LOGIC; --清零信號(hào)
EN_KEY_IN:IN STD_LOGIC; --搶答開始信號(hào) 高電平有效
A_1,B_2,C_3,D_4:IN STD_LOGIC;
ADD_1:IN STD_LOGIC; --加分信號(hào)
LEDA,LEDB,LEDC,LEDD,LED_ENDTIME:OUT STD_LOGIC;
SEC_SHI:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
SEC_GE:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
FIRST:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
FALSE:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
OUT_1:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --顯示個(gè)位十位百位
OUT_2:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
OUT_3:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END ENTITY TOP_ENTITY;
ARCHITECTURE RTL OF TOP_ENTITY IS
COMPONENT OPT IS
PORT (
CLR:IN STD_LOGIC; --復(fù)位信號(hào)
EN :IN STD_LOGIC; --搶答使能信號(hào)
A,B,C,D:IN STD_LOGIC; --搶答按鈕
LEDA:OUT STD_LOGIC;
LEDB:OUT STD_LOGIC;
LEDC:OUT STD_LOGIC;
LEDD:OUT STD_LOGIC;
FALSE:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --提前搶答警報(bào)
Q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0) --搶答成功組顯示
);
END COMPONENT OPT;
COMPONENT COUNTER IS
PORT
(
ADD_1:IN STD_LOGIC; --加分信號(hào)
CHOS:IN STD_LOGIC_VECTOR(3 DOWNTO 0); --參賽組選擇信號(hào)
A2,A1,A0:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --各組計(jì)分信號(hào)
B2,B1,B0:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
C2,C1,C0:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
D2,D1,D0:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT COUNTER;
COMPONENT OUTPUT IS --提前搶答警告
PORT
(
DIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DOUT:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT OUTPUT;
COMPONENT endtime_20 IS
PORT
(
CLK_1Hz :IN STD_LOGIC; --時(shí)鐘信號(hào)
EN_in :IN STD_LOGIC; --使能計(jì)時(shí)開始
SEC_SHI:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --秒各位 BCD 4位2進(jìn)制輸出
SEC_GE:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --秒百位 BCD 4位2進(jìn)制輸出
ENDTIME:OUT STD_LOGIC --時(shí)間到警報(bào) 接蜂鳴器
);
END COMPONENT endtime_20;
COMPONENT DISPLAY IS
PORT
(
CLK_1Hz:IN STD_LOGIC;
A2,A1,A0:IN STD_LOGIC_VECTOR(3 DOWNTO 0); --各組計(jì)分信號(hào)
B2,B1,B0:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
C2,C1,C0:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
D2,D1,D0:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
OUT_BCD1:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --輸出個(gè)十百位
OUT_BCD2:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
OUT_BCD3:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT DISPLAY;
SIGNAL Q:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL AA2,AA1,AA0:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL BB2,BB1,BB0:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL CC2,CC1,CC0:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL DD2,DD1,DD0:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
U1:OPT PORT MAP(CLR,EN_KEY_IN,A_1,B_2,C_3,D_4,LEDA,LEDB,LEDC,LEDD,FALSE,Q);
U2:COUNTER PORT MAP(ADD_1,Q,AA2,AA1,AA0,BB2,BB1,BB0,CC2,CC1,CC0,DD2,DD1,DD0);
U3:OUTPUT PORT MAP(Q,FIRST);
U4:DISPLAY PORT MAP(CLK_IN_1Hz,AA2,AA1,AA0,BB2,BB1,BB0,CC2,CC1,CC0,DD2,DD1,DD0,OUT_1,OUT_2,OUT_3);
U5:endtime_20 PORT MAP(CLK_IN_1Hz,EN_KEY_IN,SEC_SHI,SEC_GE,LED_ENDTIME);
END ARCHITECTURE RTL;
--第一搶答判斷電路的VHDL程序
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY OPT IS
PORT (
CLR:IN STD_LOGIC; --復(fù)位信號(hào)
EN :IN STD_LOGIC; --搶答使能信號(hào)
A,B,C,D:IN STD_LOGIC; --搶答按鈕
LEDA:OUT STD_LOGIC:='0'; --搶答成功對(duì)應(yīng)組的led燈點(diǎn)亮
LEDB:OUT STD_LOGIC:='0';
LEDC:OUT STD_LOGIC:='0';
LEDD:OUT STD_LOGIC:='0';
FALSE:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --提前搶答警報(bào)
Q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0) --搶答成功組顯示
);
END ENTITY OPT;
ARCHITECTURE RTL OF OPT IS
SIGNAL TMP:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL TAG:STD_LOGIC;
BEGIN
TMP<=A&B&C&D;
PROCESS(CLR,EN,A,B,C,D,TMP,TAG)
BEGIN --設(shè)置鎖存標(biāo)志位
IF CLR='1' THEN
Q<="0000";
LEDA<='0';
LEDB<='0';
LEDC<='0';
LEDD<='0';
FALSE<="0000";
TAG<='0';
ELSIF EN='0' THEN
IF TAG='0' THEN
IF A='1' THEN
FALSE(0)<='1';
END IF;
IF B='1' THEN
FALSE(1)<='1';
END IF;
IF C='1' THEN
FALSE(2)<='1';
END IF;
IF D='1' THEN
FALSE(3)<='1';
END IF;
END IF;
ELSE
FALSE<="0000";
IF TAG='0' THEN
IF TMP="1000" THEN
LEDA<='1';
LEDB<='0';
LEDC<='0';
LEDD<='0';
Q<="0001";
TAG<='1';
ELSIF TMP="0100"THEN
LEDA<='0';
LEDB<='1';
LEDC<='0';
LEDD<='0';
Q<="0010";
TAG<='1';
ELSIF TMP="0010"THEN
LEDA<='0';
LEDB<='0';
LEDC<='1';
LEDD<='0';
Q<="0011";
TAG<='1';
ELSIF TMP="0001"THEN
LEDA<='0';
LEDB<='0';
LEDC<='0';
LEDD<='1';
Q<="0100";
TAG<='1';
ELSE
LEDA<='Z';
LEDB<='Z';
LEDC<='Z';
LEDD<='Z';
Q<="ZZZZ";
END IF;
END IF;
END IF;
END PROCESS;
END RTL;
--計(jì)分電路的VHDL程序 ADD_1 ADD_5
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY ADD_1_5 IS
PORT
(
ADD_5_EN,ADD:IN STD_LOGIC; --加分信號(hào)
CHOS:IN STD_LOGIC_VECTOR(3 DOWNTO 0); --參賽組選擇信號(hào)
A2,A1,A0:OUT STD_LOGIC_VECTOR(3 DOWNTO 0):="0000"; --各組計(jì)分信號(hào)
B2,B1,B0:OUT STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
C2,C1,C0:OUT STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
D2,D1,D0:OUT STD_LOGIC_VECTOR(3 DOWNTO 0):="0000"
);
END ENTITY ADD_1_5;
ARCHITECTURE RTL OF ADD_1_5 IS
BEGIN
PROCESS(ADD,ADD_5_EN,CHOS)
VARIABLE POINTS_A2,POINTS_A1,POINTS_A0:STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
VARIABLE POINTS_B2,POINTS_B1,POINTS_B0:STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
VARIABLE POINTS_C2,POINTS_C1,POINTS_C0:STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
VARIABLE POINTS_D2,POINTS_D1,POINTS_D0:STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
BEGIN
IF ADD_5_EN='1' THEN
IF ADD='1' AND ADD'EVENT THEN
CASE CHOS IS
WHEN "0001" => FOR I IN 0 TO 4 LOOP
IF POINTS_A0="1001" THEN
POINTS_A0:="0000";
IF POINTS_A1="1001" THEN
POINTS_A1:="0000";
IF POINTS_A2="1001" THEN --十位分9
POINTS_A2:="0000"; --十位清零
ELSE
POINTS_A2:=POINTS_A2+'1';
END IF;
ELSE
POINTS_A1:=POINTS_A1+'1';
END IF;
ELSE
POINTS_A0:=POINTS_A0+'1';
END IF;
END LOOP;
WHEN "0010" => FOR I IN 0 TO 4 LOOP
IF POINTS_B0="1001" THEN
POINTS_B0:="0000";
IF POINTS_B1="1001" THEN
POINTS_B1:="0000";
IF POINTS_B2="1001" THEN --十位分9
POINTS_B2:="0000"; --十位清零
ELSE
POINTS_B2:=POINTS_B2+'1';
END IF;
ELSE
POINTS_B1:=POINTS_B1+'1';
END IF;
ELSE
POINTS_B0:=POINTS_B0+'1';
END IF;
END LOOP;
WHEN "0011" => FOR I IN 0 TO 4 LOOP
IF POINTS_C0="1001" THEN
POINTS_C0:="0000";
IF POINTS_C1="1001" THEN
POINTS_C1:="0000";
IF POINTS_C2="1001" THEN --十位分9
POINTS_C2:="0000"; --十位清零
ELSE
POINTS_C2:=POINTS_C2+'1';
END IF;
ELSE
POINTS_C1:=POINTS_C1+'1';
END IF;
ELSE
POINTS_C0:=POINTS_C0+'1';
END IF;
END LOOP;
WHEN "0100" => FOR I IN 0 TO 4 LOOP
IF POINTS_D0="1001" THEN
POINTS_D0:="0000";
IF POINTS_D1="1001" THEN
POINTS_D1:="0000";
IF POINTS_D2="1001" THEN --十位分9
POINTS_D2:="0000"; --十位清零
ELSE
POINTS_D2:=POINTS_D2+'1';
END IF;
ELSE
POINTS_D1:=POINTS_D1+'1';
END IF;
ELSE
POINTS_D0:=POINTS_D0+'1';
END IF;
END LOOP;
WHEN OTHERS => NULL;
END CASE;
END IF;
ELSE
IF ADD='1' AND ADD'EVENT THEN
CASE CHOS IS
WHEN "0001" => IF POINTS_A0="1001" THEN
POINTS_A0:="0000";
IF POINTS_A1="1001" THEN
POINTS_A1:="0000";
IF POINTS_A2="1001" THEN --十位分9
POINTS_A2:="0000"; --十位清零
ELSE
POINTS_A2:=POINTS_A2+'1';
END IF;
ELSE
POINTS_A1:=POINTS_A1+'1';
END IF;
ELSE
POINTS_A0:=POINTS_A0+'1';
END IF;
WHEN "0010" => IF POINTS_B0="1001" THEN
POINTS_B0:="0000";
IF POINTS_B1="1001" THEN
POINTS_B1:="0000";
IF POINTS_B2="1001" THEN --十位分9
POINTS_B2:="0000"; --十位清零
ELSE
POINTS_B2:=POINTS_B2+'1';
END IF;
ELSE
POINTS_B1:=POINTS_B1+'1';
END IF;
ELSE
POINTS_B0:=POINTS_B0+'1';
END IF;
WHEN "0011" => IF POINTS_C0="1001" THEN
POINTS_C0:="0000";
IF POINTS_C1="1001" THEN
POINTS_C1:="0000";
IF POINTS_C2="1001" THEN --十位分9
POINTS_C2:="0000"; --十位清零
ELSE
POINTS_C2:=POINTS_C2+'1';
END IF;
ELSE
POINTS_C1:=POINTS_C1+'1';
END IF;
ELSE
POINTS_C0:=POINTS_C0+'1';
END IF;
WHEN "0100" => IF POINTS_D0="1001" THEN
POINTS_D0:="0000";
IF POINTS_D1="1001" THEN
POINTS_D1:="0000";
IF POINTS_D2="1001" THEN --十位分9
POINTS_D2:="0000"; --十位清零
ELSE
POINTS_D2:=POINTS_D2+'1';
END IF;
ELSE
POINTS_D1:=POINTS_D1+'1';
END IF;
ELSE
POINTS_D0:=POINTS_D0+'1';
END IF;
WHEN OTHERS => NULL;
END CASE;
END IF;
END IF;
A2<=POINTS_A2;A1<=POINTS_A1;A0<=POINTS_A0;
B2<=POINTS_B2;B1<=POINTS_B1;B0<=POINTS_B0;
C2<=POINTS_C2;C1<=POINTS_C1;C0<=POINTS_C0;
D2<=POINTS_D2;D1<=POINTS_D1;D0<=POINTS_D0;
END PROCESS;
END RTL;
--顯示提前搶答組電路的VHDL程序
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY OUTPUT IS
PORT
(
DIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0); --輸入提前搶答的組號(hào)
DOUT:OUT STD_LOGIC_VECTOR(3 DOWNTO 0) --輸出提前搶答的組號(hào)
);
END ENTITY OUTPUT;
ARCHITECTURE RTL OF OUTPUT IS
BEGIN
PROCESS(DIN)
BEGIN
CASE DIN IS
WHEN"0001"=>DOUT<="0001";
WHEN"0010"=>DOUT<="0010";
WHEN"0011"=>DOUT<="0011";
WHEN"0100"=>DOUT<="0100";
WHEN OTHERS=>DOUT<="0000";
END CASE;
END PROCESS;
END RTL;
--動(dòng)態(tài)各組分?jǐn)?shù)顯示輪流顯示
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DISPLAY IS
PORT
(
CLK_1Hz:IN STD_LOGIC;
A2,A1,A0:IN STD_LOGIC_VECTOR(3 DOWNTO 0); --各組計(jì)分信號(hào)
B2,B1,B0:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
C2,C1,C0:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
D2,D1,D0:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
OUT_BCD1:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --輸出個(gè)十百位
OUT_BCD2:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
OUT_BCD3:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END ENTITY DISPLAY;
ARCHITECTURE BEHAVE OF DISPLAY IS
SIGNAL FILG:STD_LOGIC_VECTOR(2 DOWNTO 0):="000";
BEGIN
PROCESS(CLK_1Hz,FILG)
BEGIN
IF CLK_1Hz'EVENT AND CLK_1Hz='1' THEN
FILG<=FILG+'1';
END IF;
CASE FILG IS --動(dòng)態(tài)循環(huán)顯示
WHEN "000" => OUT_BCD1<="0001"; --第一輪顯示組號(hào)
WHEN "001" => OUT_BCD1<=A0; --第二輪顯示分?jǐn)?shù)
OUT_BCD2<=A1;
OUT_BCD3<=A2;
WHEN "010" => OUT_BCD1<="0010";
WHEN "011" => OUT_BCD1<=B0;
OUT_BCD2<=B1;
OUT_BCD3<=B2;
WHEN "100" => OUT_BCD1<="0011";
WHEN "101" => OUT_BCD1<=C0;
OUT_BCD2<=C1;
OUT_BCD3<=C2;
WHEN "110" => OUT_BCD1<="0100";
WHEN "111" => OUT_BCD1<=D0;
OUT_BCD2<=D1;
OUT_BCD3<=D2;
END CASE;
END PROCESS;
END ARCHITECTURE BEHAVE;
--20秒倒計(jì)時(shí) 顯示
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY endtime_20 IS
PORT
(
CLK_1Hz :IN STD_LOGIC; --時(shí)鐘信號(hào)
EN_IN :IN STD_LOGIC; --使能計(jì)時(shí)開始
SEC_SHI:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --秒各位 BCD 4位2進(jìn)制輸出
SEC_GE:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --秒百位 BCD 4位2進(jìn)制輸出
ENDTIME:OUT STD_LOGIC --時(shí)間到警報(bào) 接蜂鳴器
);
END ENTITY endtime_20 ;
ARCHITECTURE BEHAVE OF endtime_20 IS
SIGNAL CONTER_20:STD_LOGIC_VECTOR(4 DOWNTO 0):="00000";
BEGIN
PROCESS(CLK_1Hz,EN_IN)
BEGIN
IF EN_IN='1' THEN
IF CLK_1Hz='1' AND CLK_1Hz'EVENT THEN
CASE CONTER_20 IS
WHEN "00000" =>SEC_SHI<="0010"; --20
SEC_GE<="0000";
CONTER_20<=CONTER_20+'1';
ENDTIME<='0';
WHEN "00001" =>SEC_GE<="1001";--19
SEC_SHI<="0001";
CONTER_20<=CONTER_20+'1';
WHEN "00010" =>SEC_GE<="1000";--18
SEC_SHI<="0001";
CONTER_20<=CONTER_20+'1';
WHEN "00011" =>SEC_GE<="0111";--17
SEC_SHI<="0001";
CONTER_20<=CONTER_20+'1';
WHEN "00100" =>SEC_GE<="0110";--16
SEC_SHI<="0001";
CONTER_20<=CONTER_20+'1';
WHEN "00101" =>SEC_GE<="0101";--15
SEC_SHI<="0001";
CONTER_20<=CONTER_20+'1';
WHEN "00110" =>SEC_GE<="0100";--14
SEC_SHI<="0001";
CONTER_20<=CONTER_20+'1';
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