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標(biāo)題: 19進(jìn)制計(jì)數(shù)器vhdl源程序 [打印本頁(yè)]
作者: 柏林    時(shí)間: 2019-7-3 11:43
標(biāo)題: 19進(jìn)制計(jì)數(shù)器vhdl源程序
自己做的19進(jìn)制計(jì)數(shù)器，功能挺全


vhdl源程序如下:
  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.std_logic_unsigned.all;
  4. entity jishuqijian is
  5. port(clk,clr:in std_logic;
  6. shi,ge:out std_logic_vector(6 downto 0);
  7. led:buffer std_logic);
  8. end entity ;
  9. architecture bhv of jishuqijian is
  10. signal clk1:std_logic;
  11. signal shi1,ge1:integer range 0 to 9;
  12. begin
  13. process(clk)
  14. variable num:integer range 1 to 25000000;
  15. begin
  16. if rising_edge(clk)then
  17. if num=25000000 then num:=1;clk1<=not clk1;
  18.   else num:=num+1;
  19.   end if;
  20. end if;
  21. end process;
  22. process (clk1,clr)
  23. begin
  24. if clr='1' then
  25. shi1<=1;
  26. ge1<=8;
  27. led<='0';
  28. elsif rising_edge (clk1) then
  29.   if shi1=0 and ge1=0 then shi1<=1;ge1<=8;led<=not led;
  30.   elsif shi1=1 and ge1=0 then shi1<=0;ge1<=9;
  31.   else ge1<=ge1-1;
  32.   end if ;
  33.   end if;
  34.   end process;
  35.   process(shi1,ge1)
  36.   begin
  37.   case shi1 is
  38.   when 0=>shi<="1000000";
  39.   when 1=>shi<="1111001";
  40.   when others=>shi<="1111111";
  41.   end case ;
  42.   case ge1 is
  43.   when 0=>ge<="1000000";
  44.   when 1=>ge<="1111001";
  45.   when 2=>ge<="0100100";
  46.   when 3=>ge<="0110000";
  47.   when 4=>ge<="0011001";
  48.   when 5=>ge<="0010010";
  49.   when 6=>ge<="0000010";
  50.   when 7=>ge<="1111000";
  51.   when 8=>ge<="0000000";
  52.   when 9=>ge<="0010000";
  53.   when others=>ge<="1111111";
  54.   end case ;
  55.   end process;
  56.   end bhv;
復(fù)制代碼

所有資料51hei提供下載:
19jishuqijian.zip (7.53 MB, 下載次數(shù): 18)






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