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標題: 奇偶驗證碼VHDL源程序 [打印本頁]

作者: GDR 時間: 2018-11-9 16:35
標題: 奇偶驗證碼VHDL源程序
Library ieee;

Use ieee.std_logic_1164.all;

Entity mux41a is

port(s:in std_logic_vector(1 downto 0);

d0,d1,d2,d3:in std_logic;

y:out  std_logic);

End mux41a ;

Architecture ab of mux41a is

Begin

y<=d0 when s=“00”  else

d1 when s=“01”  else

d2 when s=“10”  else

d3;

End  ab;

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