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標題: Verilog實現(xiàn)00-FF [打印本頁]

作者: yyq1205 時間: 2018-7-4 10:32
標題: Verilog實現(xiàn)00-FF
module
led_seg7(clk,rst_n,sm_cs1_n,sm_cs2_n,sm_db);
input clk;    //50MHz
input rst_n;    //復(fù)位信號，低有效
output sm_cs1_n,sm_cs2_n; //數(shù)碼管片選信號，低有效
output[7:0] sm_db; //8段數(shù)碼管
reg[23:0] cnt;    //計數(shù)器，換算公式，網(wǎng)上看看
always@(posedge clk or negedge rst_n)
if(!rst_n) cnt<=24'd0;
else cnt <= cnt +1'b1;    //循環(huán)計數(shù)
reg[3:0] num;       //顯示數(shù)值
always@(posedge clk or negedge rst_n)
if(!rst_n) num<=4'd0;
else if(cnt == 23'hfffffff) num <= num +1'b1;
parameter seg0 = 8'hbf,
seg1 = 8'h86,
seg2 = 8'hdb,
seg3 = 8'hcf,
seg4 = 8'he6,
seg5 = 8'hed,
seg6 = 8'hfd,
seg7 = 8'h87,
seg8 = 8'hff,
seg9 = 8'hef,
sega = 8'hf7,
segb = 8'hfc,
segc = 8'hb9,
segd = 8'hde,
sege = 8'hf9,
segf = 8'hf1;
reg[7:0] sm_dbr;    //8段數(shù)碼管
always@(num)
case(num)    //num值顯示在倆個數(shù)碼管上
4'h0:sm_dbr<=seg0;
4'h1:sm_dbr<=seg1;
4'h2:sm_dbr<=seg2;
4'h3:sm_dbr<=seg3;
4'h4:sm_dbr<=seg4;
4'h5:sm_dbr<=seg5;
4'h6:sm_dbr<=seg6;
4'h7:sm_dbr<=seg7;
4'h8:sm_dbr<=seg8;
4'h9:sm_dbr<=seg9;
4'ha:sm_dbr<=sega;
4'hb:sm_dbr<=segb;
4'hc:sm_dbr<=segc;
4'hd:sm_dbr<=segd;
4'he:sm_dbr<=sege;
4'hf:sm_dbr<=segf;
default:;
endcase
assign sm_db = sm_dbr;
assign sm_cs1_n = 1'b0;  //數(shù)碼管1常開
assign sm_cs2_n = 1'b0;  //數(shù)碼管2常開
endmodule

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