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/*==============================================
* 描述:頻率計(jì)控制模塊計(jì)數(shù)測(cè)試程序
//==============================================*/
module frqent_count(clk_b,clk_d,vavle,rst,cnt_h_out,cnt_b_out,cnt_d_out);
input rst;
input clk_b;
input clk_d;
input vavle;
output reg[31:0] cnt_h_out; //用于測(cè)量高脈寬
output reg[31:0] cnt_b_out; //標(biāo)準(zhǔn)頻率計(jì)數(shù)
output reg[31:0] cnt_d_out; //待測(cè)頻率計(jì)數(shù)
reg [31:0] cnt_h; //用于測(cè)量高脈寬
reg [31:0] cnt_b; //標(biāo)準(zhǔn)頻率計(jì)數(shù)
reg [31:0] cnt_d; //待測(cè)頻率計(jì)數(shù)
reg start_reg; //開(kāi)始信號(hào)緩存
reg clk_d_reg; //待測(cè)時(shí)鐘緩存
wire start;
/*------------------------------------------------
* 模塊說(shuō)明:計(jì)數(shù)允許模塊
* 備注:Start_l對(duì)于頻率沒(méi)有作用,只對(duì)于低電平
脈寬計(jì)數(shù)有作用,頻率主要作用在Start
*-------------------------------------------------*/
assign start = vavle;
//開(kāi)始信號(hào)緩存
always@(posedge clk_b,negedge rst)
begin
if(!rst)
begin
start_reg <= 1'b0;
end
else
begin
start_reg <= start;
end
end
//待測(cè)信號(hào)緩存
always@(posedge clk_b, negedge rst)
begin
if(!rst)
begin
clk_d_reg <= 1'b0;
end
else
begin
clk_d_reg <= clk_d;
end
end
//待測(cè)時(shí)鐘進(jìn)行計(jì)數(shù)
always@(posedge clk_d,negedge rst)
begin
if(!rst)
begin
cnt_d <= 32'b0;
end
else
begin
if(start == 0)
begin
cnt_d <= 0;
end
// 高電平觸發(fā)
else
begin
cnt_d <= cnt_d + 1'b1;
end
end
end
//標(biāo)準(zhǔn)時(shí)鐘進(jìn)行計(jì)數(shù)
always@(posedge clk_b,negedge rst)
begin
if(!rst)
begin
cnt_b <= 0;
end
else
begin
if(start == 0)
begin
cnt_b <= 0;
end
else
begin
cnt_b <= cnt_b + 1'b1;
end
end
end
//高電平計(jì)數(shù)
always@(posedge clk_b, negedge rst)
begin
if(!rst)
begin
cnt_h <= 0;
end
else
begin
if(clk_d == 0)
begin
cnt_h <= 0;
end
else
begin
cnt_h <= cnt_h + 1'b1;
end
end
end
//標(biāo)準(zhǔn)計(jì)數(shù)和待測(cè)計(jì)數(shù)輸出
always@(posedge clk_b, negedge rst)
begin
if(!rst)
begin
cnt_b_out <= 0;
cnt_b_out <= 0;
end
else
begin
if(start_reg && !start)
begin
cnt_b_out <= cnt_b;
cnt_d_out <= cnt_d;
end
else
begin
cnt_b_out <= cnt_b_out;
cnt_d_out <= cnt_d_out;
end
end
end
//高電平計(jì)數(shù)輸出
always@(posedge clk_b,negedge rst)
begin
if(!rst)
begin
cnt_h_out<=0;
end
else
begin
if(clk_d_reg&&!clk_d)
begin
cnt_h_out<=cnt_h;
end
else
begin
cnt_h_out<=cnt_h_out;
end
end
end
endmodule

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